An interrupt is a break in the normal flow of instruction processing in a central processing unit triggered by a hardware signal from an external or internal source. Typically, a microprocessor will have a plurality of interrupt sources each of which can be enabled or triggered to execute an interrupt service routine. Each of the interrupts of the microprocessor has an assignable priority level which is typically set by default.
When two interrupts are enabled, the interrupt with the highest priority level initiates its interrupt service routine. The interrupts also have a service order so that if two interrupts having the same highest priority level are enabled, the interrupt being first in the service order initiates its interrupt service routine.
For a microprocessor having fourteen interrupts, each interrupt having four priority levels (3, 2, 1, 0) there are 414, i.e. 268,435,456 interrupt/priority level permutations and it would normally be necessary to test each of these permutations to determine whether or not all the interrupts on the microprocessor correctly function at their respective possible priority levels. The testing time required to test all permutations is unacceptable and this burden of testing would delay time to market.
Accordingly, it is an object of the present invention to seek to provide a method of testing interrupt sources in a microprocessor having interrupts with a plurality of priority levels which reduces the test burden.
Accordingly, one aspect of the present invention provides a method of testing the interrupt sources of a microprocessor having a number of interrupts which are each operable to execute an interrupt service routine when enabled, each interrupt having a default priority level and an associated memory, the interrupts having a service order in which they are to be serviced, the method comprising the steps of: a) sorting the interrupts in descending service order; b) determining an array of priority levels to be assigned in a pre-arranged sequence to selections of interrupts in descending service order, the array of priority levels consisting of: the lowest priority level; and the priority levels in descending order from the highest priority level to the lowest priority level; c) incrementing a global counter; d) assigning the array of priority levels to a selected group of interrupts, the remainder of the interrupts assuming their pre-assigned priority level; e) enabling all interrupts simultaneously so that the interrupt having the highest priority level executes its interrupt service routine; f) transferring the value of the global counter into the memory of the interrupt having executed its interrupt service routine; g) repeating steps c) to f) until the pre-arranged sequence is completed; and h) comparing the interrupt memory values after completion of the pre-arranged sequence with expected values and determining from the comparison whether there is an error in the microprocessor interrupts.
Preferably, the array of priority levels is assigned to a first group of interrupts and then subsequently to other groups of interrupts in descending service order.
Conveniently, the first assignment of the array of priority levels to a selected group of interrupts comprises assigning the highest priority level in the array to the interrupt being last in the service order, the first priority level in the array being the lowest priority level not being assigned to an interrupt and the remainder of the priority levels in the array being assigned to the remainder of the interrupts in the selected group of interrupts in descending service order.
Advantageously, the first repetition of step (d) assigns the first priority level of the array, the lowest priority level, to the interrupt being last in the service order, the remainder of the priority levels in the array being assigned to the remainder of the interrupts in the selected group of interrupts.
Preferably, subsequent repetitions of step (d) assign the first of the priority levels of the array to the next interrupt in descending service order until the first priority level of the array has been assigned to every interrupt, and the final repetition assigns the default priority levels to the interrupts, thereby marking the end of the pre-arranged sequence.
Conveniently, there are four priority levels: 3; 2; 1; and 0, 3 being the highest priority level and 0 being the lowest priority level, the array of priority levels therefore comprising: 0;3:2;1;0.
Advantageously, the global counter has an initial value of 0 and step c) of incrementing the global counter comprises the step of incrementing the global counter by one.
Preferably, the number of repetitions of steps c) to f) is greater than the number of interrupts.
Conveniently, the microprocessor has 14 interrupts with 4 priority levels, 16 repetitions of steps c) to f) being required to complete the sequence.
Advantageously, the pre-arranged sequence requires at least the highest priority level in the array to be assigned to each of the interrupts in descending service order.
In order that the present invention may be more readily understood, embodiments thereof will now be described, by way of example, with reference to the accompanying drawings.